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Milestones for Semester
II
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| 1.Synthesize for
a range of different architectural features on two technologies ASIC (library
required) and FPGA. |
| 2.Looking
at the synthesis results, prepare a model for estimation of area and clock
period. Orthogonolity and interlinkages between different parameters to
be studied. |
| 4.A VHDL generator
which inputs the configuration and writes the synthesizable VHDL |
| 5.Validate the generated
VHDL by actually implementing on the Virtex platform |
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